1. Field of the Invention
This invention relates to compact static random access memories that use self aligned contacts and split word lines.
2. Description of Related Art
Application Ser. No. 07/555,559, filed Jul. 19, 1990, entitled "Compact SRAM Cell Layout", now U.S. Pat. No. 5,124,774, which is a continuation-in-part of Ser. No. 07/464,496 filed on Jan. 12, 1990, entitled "Self-aligning Contact and Interconnect Structure", now U.S. Pat. No. 5,166,771 have the same assignee as the present application, and cover formation of self aligned contacts. This application incorporates by reference the above-mentioned applications Ser. No. 07/555,559 and 07/464,496. This application is related to and also incorporates by reference: application Ser. No. 07/464,094, filed Jan. 12, 1990 and entitled "High Resistance Polysilicon Load Resistor", now U.S. Pat. No. 5,172,211; application Ser. No. 7/724,008, filed Jul. 1, 1991, entitled "Method of Fabricating a High Resistance Polysilicon Load Resistor", now U.S. Pat. No. 5,168,076; and Ser. No. 07/984,666, filed Dec. 2, 1992, entitled "Transistor Fabrication Methods and Methods of Forming Multiple Layers of Photoresist", all of which have the same assignee as the present application.
A static random access memory (SRAM) typically includes an array of memory cells. In one such cell as shown in FIG. 1, the cell has two possible states indicated by the voltage levels at two nodes 103, 104. Typically, a static memory cell includes two pull-down transistors 101, 102 having their sources connected to a reference potential V.sub.SS and their gates and drains cross coupled such that the drains 103, 104 of the pull-down transistors 101, 102 are connected to the gates of transistors 102, 101, respectively. Each of the nodes 103, 104 is also connected to a pull-up device 105, 106. Each pull-up device 105, 106 may take the form of a load resistor or a pull-up transistor which connects between an operating potential V.sub.CC and the corresponding node 103, 104.
Pass transistors 107, 108 connect the nodes 103, 104 to bit lines BL, BL. The same bit lines, BL and BL, connect to a number of memory cells that are arranged in a column. The gates of the pass transistors 107, 108 are typically connected to a word line WL, and the same word line WL connects to a number of memory cells that are arranged in a row.
A memory includes an array of memory cells, each cell as described above, with a grid formed from a set of parallel word lines that crosses a set of parallel bit lines. From this array, a desired cell is accessed by asserting a voltage to the word line connected to the desired cell. This causes all the pass transistors connected to this word line WL to conduct. The voltage levels of the bit lines BL, BL connected though the conducting pass transistors to nodes 103, 104 of the desired memory cell, change according to whether the pull-down transistor 101 or 102 is conducting. The state of the desired memory cell can then be read by sensing the voltage difference that develops between the bit lines BL, BL or the desired cell may be written to by asserting voltages to the bit lines BL, BL which connect to the desired cell.
Two goals of memory fabrication are to reduce memory size and increase manufacturing yield. Size reduction permits more memory cells to be placed on a chip, and generally lowers manufacturing cost by reducing the amount of silicon "real estate" required to make a memory. Higher manufacturing yield directly reduces per unit cost by providing more usable product for a fixed fabrication cost. Many techniques have been developed to achieve these goals.
One technique is efficient layout of memory cell elements. Generally, the layout of the elements in a memory cell is restricted by the manufacturing requirements. For example, contacts between various layers in an integrated circuit memory cell must be aligned, and separation must be provided between elements that require isolation.
During manufacturing, alignment of consecutive layers of an integrated circuit is imperfect, so tolerances must be incorporated into a memory cell layout. Also, elements on layers of an integrated circuit must have minimum separations to permit etching without stringers of conductive material being left between regions that should be isolated. These manufacturing concerns require the separation between elements and the size of contacts be sufficient to produce a working circuit even with expected misalignments and etching limitations.
With the manufacturing requirements in mind an efficient layout makes the memory cell as compact as possible. A problem with prior art memory cells is irregularly shaped elements that must be isolated from other elements in the cell. Active regions with protruding connections have larger perimeters for the same current carrying capacity when compared to regions without protrusions. The size of the surrounding isolation region depends on the length of the perimeter and hence also tends to be larger. An efficient layout positions and shapes the elements of a memory cell so that isolation regions are minimized while the critical separations remain sufficient.
FIG. 2 shows the layout of two layers of a typical SRAM cell. Two types of region are shown, active regions in a silicon substrate and regions formed from a first polysilicon layer. Active regions 201, 202 are used to form pull-down transistors. As part of a first doped polycrystalline silicon layer (poly-1) a region 211 forms a gate 211a for a pull-down transistor formed from the region 201. Region 211b is an interconnect that connects the gate 211a to the node 204a, and region 211c is an interconnect between the gate 211a and the drain 202a of the pull-down transistor formed from the active region 202. Poly-1 region 212 forms a gate 212a for a pull-down transistor formed from the region 202 and connects the gate 212a to node 201a and the drain 201c of pull-down transistor formed in region 201. Poly-1 region 213 forms the word line WL and gates 213a and 213b for pass-transistors formed from the active regions 201 and 204.
Contacts 211b, 211e, and 212b in poly-1 regions 211, and 212 connect from the poly-1 layer to the active region beneath. Contacts 201b, 204b in active regions 201, 204 are for connection to bit lines which are formed on a layer not shown. The contact areas 211d, 211e, 212b, 201b, 204b must be relatively large to compensate for expected manufacturing misalignment.
One technique for reducing the required minimum separations and minimum contact size is to use self aligned contacts. Examples of the structure of a self aligned contact and then techniques for forming a self aligned contact are described in "Self-aligning Contact and Interconnect Structure", U.S. Pat. No. 5,166,771 and "Compact SRAM Cell Layout", U.S. Pat. No. 5,124,774 which were incorporated by reference.
Another concern which can be addressed by efficient memory cell layout is stability of the cell. Generally, the layout of a memory cell, such as the cell shown in FIG. 2, is not physically symmetric. Asymmetry in the layout of cell elements causes asymmetry in performance of individual elements and in performance of the cell as a whole. For example, pull-down transistors formed from regions 201 and 202 may have different characteristics caused by differences in the shape of the active regions 201 and 202. Lack of symmetry causes the memory cell to have a preferred state where a particular node 201a or 204a is at the higher voltage. During a read of a memory cell or other operation, the memory cell can erroneously switch (be unstable) from its correct state to the preferred state. Asymmetric cells therefore have a greater chance of error.
Perfectly symmetric (stable) cells do not have a preferred state because there is no physical basis for distinguishing one node from another. In actual memory cells perfect symmetry cannot be achieved, but greater symmetry improves stability and a symmetric cell layout is desirable.
The typical memory cell described above has a single word line WL which connects to (or actually forms) both gates of the pass transistor. For a straight word line this requires that the gates of the pass transistors be in a line. Straight or nearly straight word lines, as shown in FIG. 2, are convenient for memories with cells arranged in a square or rectangular array and are commonly employed.
Instead of a single word line, some memory cell layouts employ a split word line. For these memory cells, the split word line includes a first and a second word line. The first word line connects to (or forms) the gate of the first pass transistor, the second word line connects to (or forms) the gate of the second pass transistor. The two word lines can be electrically coupled together outside the cell so that the split word line acts as a single line which activates both pass transistors simultaneously. With a split word line the layout of a memory cell no longer requires that the pass transistors (corresponding to pass transistors 107 and 108 in FIG. 1) be in a line or nearly in a line. Instead for example the pass transistors can be located on opposite sides of the cell.
FIG. 3 shows a layout of a prior art memory cell with split word lines WL1, WL2. Active regions 301 and 302 form the pull-down transistors and pass transistors. The split word lines WL1, WL2 form the gates 313a, 314a of the pass transistors. Poly-1 regions 311, 312 form gates 311a, 312a of the pull-down transistors and serve as interconnects to cross-couple the gates 311a, 312a and drains of the pull-down transistors. As seen in FIG. 3, the pass transistors and the contacts 301a, 302a to the bit lines are formed on opposite sides of the memory cell, and the overall layout of the cell is symmetric.